The VCS Verification Library includes verification IP for the industry's most popular bus protocols, including AMBA(TM) 3 AXI(TM), AMBA 2.0, PCI Express(R), USB, Serial ATA and 10G Ethernet, as well as more than 10,000 memory models. The verification IP includes traffic generators, and monitors to provide functional coverage of bus protocols and identify protocol violations.

The VCS Verification Library provides extensive support for the Synopsys Reference Verification Methodology (RVM), which was developed by verification experts to help engineers adopt industry-best practices for the development of interoperable and reusable verification environments. RVM uses coverage-driven and constrained-random techniques with support for the industry-standard SystemVerilog and OpenVera(R) hardware verification languages.

The VCS Verification Library is supported by VCS' Native Testbench (NTB) technology which compiles VCS Verification Library IP, testbench, assertions and design-under-test together into a single high-performance executable. By natively integrating these technologies, designers can achieve a shorter verification cycle with up to five times faster runtime performance.

"Using Synopsys' verification IP helped accelerate the development of our constrained-random testbench environment which enabled us to obtain high functional coverage and identify corner case design bugs," said Randy Mullin, director of verification at Tundra Semiconductor Corporation. "VCS NTB is an integral part of our verification process."

"As the standard interfaces on SoC designs continue to increase in number and complexity, designers are faced with tremendous verification challenges," said Guri Stark, vice president of Marketing, Synopsys' Solutions Group. "Synopsys is leading the way in solving these challenges with a product that simplifies testbench creation, provides better coverage and delivers much higher verification performance."

Availability

The VCS Verification Library is available now. Current customers of DesignWare verification IP can gain access to the new functionality at no additional charge by downloading the latest version from the Synopsys web site.

About VCS Verification Library

The VCS(R) Verification Library provides the broadest portfolio of design-proven, standards-based verification IP (VIP) helping designers save testbench development time and reach functional coverage goals faster. It offers advanced functionality for block and chip-level verification and is an integral part of the Synopsys Discovery(TM) Verification Platform. VCS Verification Library supports Verilog, SystemVerilog, OpenVera, and VHDL testbenches. It supports all popular simulators and enables up to five times faster verification when used with the VCS solution or Pioneer-NTB tool. The VCS Verification Library includes: PCI Express, PCI-X(R), PCI, USB 1.1/2.0/OTG, AMBA 2.0, AMBA 3 AXI, 10/100/1G/10G Ethernet, I2C, SATA, Serial I/O standard protocols and more than 10,000 memory models and more. For more information on the VCS Verification Library, visit: www.synopsys.com/products/solutions/discovery_platform.html

About Synopsys

Synopsys, Inc. is a world leader in EDA software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at www.synopsys.com

NOTE: Synopsys, DesignWare, OpenVera, Vera and VCS are registered trademarks of Synopsys, Inc. Discovery is a trademark of Synopsys. AMBA and AXI are trademarks of ARM Limited. PCI, PCI-X and PCI Express are trademarks of PCI-SIG. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners. Statements contained on Synopsys' website shall not be deemed incorporated into this press release.

    Editorial Contacts:
     Troy Wood
     Synopsys, Inc.
     650-584-5717
     Email Contact

     Melissa Chanslor
     Edelman
     650-429-2797
     Email Contact

CONTACT: Troy Wood of Synopsys, Inc., +1-650-584-5717, or
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